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Features
* * * * * * * * * * * * *
4-bit HARVARD Architecture 4 k 8-bit Application ROM 256 4-bit RAM 32 16-bit EEPROM 10 Bi-directional I/Os 4 External Interrupt Inputs (SSO20) 8 Interrupt Levels 2 8-bit Multifunction Timer/Counter Interval Timer with Watchdog Two-Wire Interface (TWI) Voltage Supervisor On-chip RC Oscillator On-chip Crystal Oscillator
Benefits
* * * * * * * * *
Contactless Power Supply and Communication Interface Power Management for Contactless and Battery Power Supply Shift-register-supported Modulator and Demodulator Stages Low Power Consumption Active Mode < 300 A at 2 V and 1 MHz System Clock Frequency (2 s Instruction Cycle) Power-down Mode < 1 A Supply Voltage 2.0 V to 6.5 V High-level Language Programming in qFORTH Operating Speed: 1 s to 10 s Instruction Cycle (2 s at VDD = 2 V)
Microcontroller with Transponder Interface U9280M-H Preliminary
Description
The U9280M-H IC is a multi-chip module for remote control and contactless ID systems. It consists of the ATAR092 microcontroller and U3280M transponder interface circuit with EEPROM. A coil connected to the transponder interface serves as a wireless bi-directional communication interface as well as a power supply for the microcontroller and the interface. As a transponder, the device is supplied by a magnetic RF field applied at the coil. For IR- or RF-transmitter applications, it can be supplied by a battery. The microcontroller supports, with its built-in timers, a wide range of IR- and RF-transmission modes such as burst-modulation modes, PWM-, NRZ-, Manchester- and Bi-phase coding.
Rev. 4591A-RFID-03/03
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Figure 1. Block Diagram
C
OSC2 VBATT VDD OSC1/ROSC
U9280M-H transponder interface
Damping stage Field/GAP detect COIL1 Rectifier 512-bit EEPROM memory Power management
ATAR092 microcontroller
Reset voltage monitor Oscillators clock management
ROM
RAM Timer/ counter
BP50/INT6 BP53/INT1 BP23 BP20/NTE
4-bit CPU core
MCL
COIL2 Clock extractor
1
Serial interface Biphase modulator
Serial interface
Modulator/ demodulator I/O-Ports
BP60/T3O BP63/T3I
VSS FC NGAP MOD BP40/ SC/INT3 BP43/ SD/INT3 BP42/ T2O BP41/ VMI/ T2I
Pin Configuration
Figure 2. Pinning SSO20
COIL1 COIL2 VBATT VDD BP40/SC/INT3 BP53/INT1 BP50/INT6 OSC1/ROSC OSC2 BP60/T3O
1 2 3 4 5 6 7 8 9 10
20 19 18 17
NGAP MOD FC VSS BP43/SD/INT3 BP42/T2O BP41/VMI BP23 BP20/NTE BP63/T3I/INT5
U9280M-H
16 15 14 13 12 11
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Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol COIL1 COIL2 VBATT VDD BP40/SC/INT3 BP53/INT3 BP50/INT6 OSC1/ROSC OSC2 BP60/T3O BP63/T3I/INT5 BP20/NTE BP23 BP41/VMI BP42/T2O BP43/SD/INT3 VSS FC MOD NGAP Function Coil input 1, Pin to connect an LC antenna for communication and field supply Coil input 2, Pin to connect an LC antenna for communication and field supply Power-supply voltage input to connect a battery Power-supply voltage for the microcontroller and EEPROM. At this pin a capacitor (0.5 F to 10 F) must be connected to buffer the voltage during field supply and to block the VDD of the microcontroller. I/O-port line/serial clock line/INT3 input (falling edge sensitive) I/O-port line/INT3 interrupt input (falling or rising edge sensitive) I/O-port line/INT6 interrupt input (falling or rising edge sensitive) Oscillator- or external system-clock input/input for RC-oscillator resistor Oscillator output Bi-directional I/O-line/Timer 3 output/modulator output I/O-port line/INT5 interrupt input/Timer 3 input/demodulator input BP20-I/O-port line/test mode input. This input is used to control the test modes. During POR it must not be connected with a low impedance to VDD. I/O-port line I/O-port line/Voltage monitor input/Timer 2 input I/O-port line/Timer 2 output/modulator output I/O-port line/serial data line/INT3 input (falling edge sensitive) Circuit ground Field clock output of the clock extractor Modulation input - front end. Must be connected to the modulator output T2O. Gap detect output - front end. Must be connected to the demodulator input T3I.
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Functional Description
The U9280M-H multi-chip module contains a microcontroller and a transponder IC mounted in a single package. Everything necessary for remote control and wireless identifcation systems is integrated: Inputs to connect keys, outputs to control an IR- or RF transmitter and to drive indicator LEDs, an EEPROM to store key code and identifiers, and an interface for contactless communication and a power supply. The U3280M is a transponder interface consisting of an analog front end for contactless data communication and power supply, and a serial 512-bit EEPROM. In addition, it includes power management to switch the battery or magnetic-field power supply. For modulation and demodulation of the magnetic field, the device has input and output pins to connect the microcontroller. The MOD, NGAP and FC Pins can be connected externally to the modulator, demodulator and timer I/O pins of the microcontroller. Access to the EEPROM is possible via a two-wire serial interface. The ATAR092 microcontrollers are equipped with compatible two-wire serial interface to communicate with the U3280M. In the U9280M-H the serial interfaces of the transponder interface and the microcontroller are linked internally.
ATAR092
The ATAR092 microcontroller is a member of the Atmel's 4-bit single-chip microcontroller family. It is especially designed for remote-control applications. It consists of an advanced stack-based 4-bit CPU core with 4 K ROM, 256 nibble of RAM and on-chip peripherals. The CPU is based on the HARVARD architecture and contains an interrupt controller with 8 prioritized interrupt levels. The peripherals include parallel I/O ports, two 8-bit programmable multifunction timer/counters, a two-wire serial interface, an interval timer with watchdog function and a voltage supervisor. The serial interface supports, together with the timers, a modulator and demodulator stage for Manchester, Bi-phase and pulse-width modulation and demodulation. The integrated clock generator contains a RC-, a 32-kHz crystal, a 4-MHz crystal oscillator and a programmable input to use an external clock.
Note: In the U9280M-H not all I/O pins of the ATAR092 are available (see "Pin Description"). The microcontroller is fully described in the MARC4 ATAR092 data sheet.
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Figure 3. Block Diagram ATAR092
V SS V DD OSC1 OSC2
Brown-out protect RESET Voltage monitor External input VMI BP10 Port 1 BP13 BP20/NTE
RC Crystal External oscillators oscillators clock input Clock management
UTCM Timer 1 interval- and watchdog timer Timer 2 8/12-bit timer with modulator SSI
T2I T2O SD
ROM
4 K x 8-bit
RAM
256 x 4 bit
MARC4
Data direction Port 2
Serial interface Timer 3 8-bit timer / counter with modulator and demodulator
SC
BP21 BP22 BP23
4-bit CPU core I/O bus
T3O T3I
Data direction + alternate function Port 4
Data direction + interrupt control Port 5
Data dir. + alt. function Port 6
BP50 BP52 BP40 BP42 INT3 T2O BP43 INT6 INT1 SC BP41 BP53 BP51 INT3 VMI INT6 INT1 SD T2I
BP60 BP63 T3O T3I
The U3280M Transponder Interface
The transponder interface contains a rectifier stage to rectify the AC from the coil inputs and to supply itself and an additional microcontroller device with power from an LC-resonant circuit at the coil inputs. It is also possible to supply the device via the VBatt -input with DC from a battery. The built-in power management switches automatically between battery supply (VBatt pin) and coil supply. It switches to coil supply if a field is applied at the coil and switches back to battery if the field is removed. The voltage from the coil or the VBatt pin is output at the VDD pin to supply the microcontroller device. At the VDD pin a capacitor must be connected to smooth and buffer the supply voltage for the transponder interface and the microcontroller. This capacitor is also used to buffer the supply voltage during communication (damping and gaps in the field). For communication, a damping-stage and a gap-detect circuitry is on the chip. By means of the damping stage the coil voltage can be modulated to transmit data via the field. It can be controlled with the modulator input (MOD pin) via the microcontroller. The gap detection circuitry detects gaps in the field and outputs the gap/field signal at the gap detect output (NGAP pin). It can be used to receive data via a modulated field and to check if a field is applied at the coil. For the storage of data such as key codes, identifiers and configuration bits, a 512-bit EEPROM is available on the chip. It can be read and written to by the microcontroller via a TWI-compatible two-wire serial interface. The serial interface, the EEPROM and the microcontroller are supplied with the voltage at the VDD pin. That means the microcontroller can read and write to the EEPROM if the supply voltage is in the operating range.
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The U3280M contains additional operating modes to support a wide range of applications. These modes can be controlled via the serial interface. The power management can be switched off by software to disable the automatic switching between battery and field. This supports applications with battery supply only. There is an on-chip Bi-phase and Manchester modulator. It can be selected and controlled via the serial interface with a special mode control byte. If this modulator is used the external connection to the modulator input is not necessary.
Modulation
The transponder interface can modulate the magnetic field by a modulator to transmit data to a base station. It modulates the coil voltage by varying the coil`s load. The modulator can be controlled via the MOD pin. A high level 1 increases the current into the coil inputs and damps the coil voltage. A low level 0 decreases the current and increases the coil voltage. The modulator generates a voltage stroke of about 2 Vpp at the coil. A high level at the MOD input makes the maximum of the field energy available at VDD. During a reset a high level at the MOD input causes the optimum conditions for starting the device and charging the capacitor at VDD after the field is applied at the coil. Mod = 0: coil undamped V COIL_peak = V DD 2 + V CMS = V CU Mod = 1: coil damped V COIL_peak = V DD 2 = V CD VCMS = VCID: modulation voltage stroke at coil inputs
Note: If the automatic power management is disabled the internal front end VDD is limited at VDDC. In this case the value VDDC must be used in the formula above.
Digital Input to Control the Damping Stage (MOD)
Field Clock
The field clock extractor of the interface makes the field clock available for the microcontroller. It can be used to supply timer inputs to synchronize modulation and demodulation with the field clock. The transponder interface can also receive data. The base station modulates the data with short gaps in the field. The gap-detection circuit detects these gaps in the magnetic field and outputs the gap/field signal at the NGAP pin. A high level indicates that a field is applied at the coil and a low level indicates a gap or that the field is off. The microcontroller must demodulate the incoming data stream at one of its inputs. NGAP = 0: gap detected/no field VCOIL_peak = VFDOFF NGAP = 1: field detected VCOIL_peak = VFDON
Note: No amplifier is used in the gap detection stage. A digital Schmitt trigger evaluates the rectified and smoothed coil voltage.
Gap Detect
Digital Output of the Gap Detection Stage (NGAP)
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Wake-up Signal
If a field is applied at the coil of the transponder interface the microcontroller can be woken up with the wake signal at the NGAP pin. For that purpose the NGAP pin must be connected to an interrupt input of the microcontroller. A high level at the NGAP output indicates an applied field and can be used as a wake signal for the microcontroller via an interrupt. If no battery voltage is available at VBatt the controller starts with a poweron-reset after the voltage of the buffer capacitor at VDD is loaded by the field above the power-on-reset level. The wake signal is generated if the power management switches to field supply. The field detection stage of the power management has low-pass characteristics to avoid the generation of wake signals and unnecessary switching between battery and field supply in case of interferences at the coil inputs.
U3280M Signals and Timing
Figure 4. Modulation
MOD
VCU V CMS Coil inputs VCD
Figure 5. Gap Detection and Battery to Field Switching
t FGAP1 t FGAP1 VV FDON FDON
Coil inputs
t FGAP0 t FGAP0
Coil inputs
V VFDOFF
FDOFF
1. edge used as 1. edge used signal wakeupas wakeup signal
NGAP
NGAP
Field clock Fieldclock FC FC
Power management Power management
Battery supply
Battery supply
t BFS BFS t
Battery
Coil supply if automatically power Coilsupply if automatically power management is enabled management is enabled
supply
Battery supply
tFBSFBS t
Power Supply
The U3280M has a power management that handles two power-supply sources. Normally, the IC is supplied by a battery at the VBatt pin. If a magnetic field is applied at the LC-resonant circuit of the device the field detection circuit switches from VBatt to field supply. During field supply the VDD voltage is limitted to 3 V. The VDD pin is used to connect a capacitor to smooth the voltage from the rectifier and to buffer the power when the field is modulated by gaps and damping. The EEPROM and the microcontroller always operate with the voltage at the VDD pin. 7
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Automatic Power Management
There are different conditions to switch from the battery to field generated voltage and vice versa. Figure 6. Switch Conditions for Power Management
VCoil < VFDON for t > tFBS
Battery supply (VBatt)
Field supply
VCoil < VFDOFF for t > tFBS
The power management switches automatically from battery to field if the rectified voltage (Vcoil) from the coil inputs becomes higher than field-on-detection voltage (VFDON) even if no battery voltage is available (0 < VBatt < 1.8 V). It switches back to battery if the coil voltage becomes lower than the field-off-detection voltage (VFDOFF). The field-detection stage of the power management has low-pass characteristics to suppress noise. An applied field needs a time delay tBFS (battery-to-field switch delay) to change the power supply. If the field is removed from the coil the power management will generate a reset of the microcontroller. Controlling Power Management via the Serial Interface The automatic mode of the power management can be switched off and on by a command from the microcontroller. If the automatic mode is switched off the IC is always supplied by the battery up to the next power-on reset or to a switch-on command. The power management-on and -off command must be transferred via the serial interface. If the power management is switched off and the device is supplied from the battery it can communicate via the field without loading the field. This mode can be used to realize applications with a battery supply if the available field is too weak to supply the IC with power. Buffer Capacitor CB The buffer capacitor connected at VDD is used to buffer the supply voltage for the microcontroller and the EEPROM during field supply. It smooths the rectified AC from the coil and buffers the supply voltage during modulation and gaps in the field. The size of this capacitor depends on the application. It must be of a dimension so that during modulation and gaps the ripple on the supply voltage is in the range of 100 to 300 mV. During gaps and damping the capacitor is used to supply the device, that means the size of the capacitor depends on the length of the gaps and damping cycles. Example: For a supply current of 350 A, 200 mV ripple at VDD Table 1. Buffer Capacitor
Time with no Field Supply Necessary CB
250 s 500 s
470 nF 1000 nF
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Serial Interface
The transponder interface has an serial interface to the microcontroller for read and write accesses to the EEPROM. In a special mode the serial interface can also be used to control the Bi-phase/Manchester modulator or the power management of the U3280M. The serial interface of the U3280M device must be controlled by a master device (normally the ATAR09x microcontroller) which generates the serial clock and controls the access via the SCL- and SDA-line. SCL is used to clock the data in and out of the device. SDA is a bi-directional line used to transfer data into and out of the device. The following protocol is used for data transfers. Serial Protocol * * * * * Data states on the SDA line changing only while SCL is low. Changes in the SDA line while SCL is high will be interpreted as a START or STOP condition. A START condition is defined as a high-to-low transition on the SDA-line while the SCL-line is high. A STOP condition is defined as a low-to-high transition on the SDA-line while the SCL-line is high. Each data transfer must be initialized with a START condition and terminated with a STOP condition. The START condition wakes the device from standby mode and the STOP condition returns the device to stand-by mode. A receiving device generates an acknowledge (A) after the reception of each byte. For that the master device must generate an extra clock pulse. If the reception was successful the receiving master or slave device pulls down the SDA-line during that clock cycle. If in transmit mode an acknowledge is not detected (N) by the interface, it will terminate further data transmissions and will go into receive mode. A master device must finish its read operation by a Not-acknowledge and then issue a stop condition to place the device into a known state.
*
Figure 7. Serial Protocol
SCL SDA Stand- Start by condition Data valid Data/ Data change acknowledge valid Stop Standcondition by
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Control Byte Format
EEPROM address Start A4 A3 A2 A1 A0 Mode control bits C1 C0 Read/Write R/W Ackn
The control byte follows the start condition and consists of the 5-bit row address, 2 mode control bits and the read/not writebit. Data Transfer Sequence
Start Control byte Ackn. Data byte Ackn. Data byte Ackn. Stop
* *
Before the START condition and after the STOP condition the device is in standby mode and the SDA-line is switched to input with a pull-up resistor. The START condition follows a control byte that determines the following operation. Bit 0 of the control byte is used to control the following transfer direction. A 0 defines a write access and a 1 a read access.
EEPROM
The EEPROM has a size of 512 bits and is organized as a 32 16-bit matrix. To read and write data to and from the EEPROM the serial interface must be used. The interface supports one and two byte write accesses and one to n-byte read accesses to the EEPROM. The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/write bit that is used to control the direction of the following transfer. A 0 defines a write access and a 1 a read access. The five address bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which order the accesses to the buffer are performed: High byte - low byte or low byte - high byte. The EEPROM also supports autoincrement and autodecrement read operations. After sending the start address with the corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses. Two special control bytes enable the complete initialization of EEPROM with a 0 or with a 1.
Operating Modes
Write Operations
The EEPROM allows 8-bit and 16-bit write operations. A write access starts with the START condition followed by a write control byte and one or two data bytes from the master. It is completed via the STOP condition from the master after the acknowledge cycle. If the EEPROM receives the control byte, it loads the content of the addressed memory cell into a 16-bit read/write buffer. After the first data byte has been received the EEPROM starts the internal programming cycle. It consists of an erase cycle (write "zeros") and the write cycle (write "ones"). Each cycle takes about 10 ms. The write cycle is started after the stop condition and the complete buffer is stored back automatically to the EEPROM. That means for two-byte write operations, the second byte must be transferred within the erase cycle otherwise only the first byte will be stored in the EEPROM and the second byte will be ignored.
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Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to detect the end of the write cycle. The master must perform acknowledge polling by sending a start condition followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform further acknowledge polling sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle.
Write One Data Byte
Start Start Start Note:
Control byte Control byte Control byte
A A A
Data byte 1 Data byte 1 Stop
A A
Stop Data byte 2 A Stop
Write Two Data Bytes Write Control Byte Only
A = acknowledge
Write Control Bytes
MSB
Write low byte first
LSB A3 A2 A1 A0 C1 0 C0 1 R/W 0
A4
Row address
Byte order
LB(R)
HB(R)
MSB
Write high byte first
LSB A3 A2 A1 A0 C1 1 C0 0 R/W 0
A4
Row address
Byte order
HB(R)
LB(R)
Note:
HB: high byte; LB: low byte; R: row address
Read Operations
The EEPROM allows byte-, word- and current address read operations. The read operations are initiated in the same way as write operations. Every read access is initiated by sending the START condition followed by the control byte which contains the address and the read mode. After the device receives a read command it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte if it wants to proceed with the read operation. If two bytes are read out from the buffer the device increments respectively, decrements the word address automatically and loads the buffer with the next word. The read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. If the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition.
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Read One Data Byte
Start Start
Read n Data Bytes
Control byte Control byte
A A
Data byte 1 Data byte 1
N A
Stop Data byte 2 N Stop
Read Two Data Bytes
Start
Control byte
A
Data byte 1 Note:
A
Data byte 2
A
-
Data byte n
N
Stop
A -> acknowledge, N -> no acknowledge
Read Control Bytes
MSB
Read low byte first, address increment
LSB A3 A2 A1 A0 C1 0 C0 1 R/W 1
A4
Row address
Byte order
LB(R)
HB(R) MSB
LB(R+1)
HB(R+1)
-
LB(R+n)
HB(R+n) LSB
Read high byte first, address decrement
A4
A3
A2
A1
A0
C1 1
C0 0 HB(R-n)
R/W 1 LB(R-n)
Row address
Byte order
HB(R)
LB(R)
HB(R-1)
LB(R-1)
-
Note:
HB: high byte; LB: low byte, R: row address
Initialization after a Reset Condition
The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrollers that have their own reset circuitry for power-on reset, watchdog reset or brown-out reset, it may be necessary to bring the EEPROM into a known state independent of its internal reset. This is performed by reading one byte without acknowledgeing and then generating a stop condition. By means of special control bytes, the serial interface can be used to control the modulator stage or power management. The EEPROM access and the serial interface are disabled in these modes until the next STOP condition. If no START or STOP condition is generated, the SCL and SDA line can be used for the modulator stage. SCL is used for the modulator clock and SDA is used for the data. In that mode, the same conditions for clock and data changing normally are valid. The SCL and SDA line can be used for continuous bit transfers, an acknowledge cycle after 8 bits must not be generated. Table 2. Special Modes
Control Byte Description
Special Modes
1100x111b 1101x111b 11xx0111b 11xx1111b xxxxx110b
Bi-phase modulation Manchester modulation Switch power management off: disables switching from battery to field supply Switch power management on: enables automatically switching between battery and field supply Reserved
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Data Transfer Sequence for Bi-phase and Manchester Modulation:
Start Control byte Ackn Note: Bit 1 Bit 2 Bit 3 ... Bit n Stop
After a reset of the microcontroller, it is not known if the transponder interface has been reset, too. It could still be in a receive or transmit cycle. To place the serial interface of the device into a known state, the miocrocontroller should read one byte from the device without acknowledge and generate a stop condition.
Power-on Reset
The analog front end starts working with the applied field. The EEPROM with the serial interface has its own reset circuitry. (The reset level of the front end is below the reset level of the ATAR092) The microcontroller has a power-on reset circuitry with a brown-out detection. One of two reset voltage levels [1.8 V/2.0 V] can be selected via the software (see the ATAR092 data sheet). If a fast instruction cycle (< 2 s) is used the higher reset level should be selected. After a watchdog or brown-out detection reset, the serial interface and the EEPROM should be reset by reading one byte from the transponder interface device without acknowledgeing and generation of a STOP condition. That places the serial interface and EEPROM into a known state.
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Electrical Characteristics - Common Features U9280M-H
* Operating Temperature Range: -40C to +85C * Operating Voltage Range (VBatt): 2.0 V to 6.5 V * Low Power Consumption:
- 600 A at 6.5 V in Operating Mode ( with 2 s Instruction Cycle) - 200 A at 2.0 V in Operating Mode (with 2 s Instruction Cycle) - 1 A at 2.0 V in Stop Mode * Power Supply: Contactless (Coil 125 kHz) and Battery Supply
Absolute Maximum Ratings
Voltages are given relative to VSS
Parameters
Symbol Value Unit
Supply voltage Maximum current out of the VSS pin Maximum current out of the VBatt pin Input voltage (on any pin) Input/output clamp current (VSS > Vi / Vo > VDD) Minimum ESD protection (100 pF through 1.5 kW) Minimum ESD protection Coil 1 and Coil 2 inputs (100 pF through 1.5 kW) Operating temperature range Storage temperature range Soldering temperature (t 10 s) Note:
VBatt,VDD
0 to +7 with reverse protection 15 15
V mA mA V mA kV kV
C C C
VIN IIK/IOK
VSS- 0.6 < VIN < VDD + 0.6 15 2 1
Tamb Tstg Tsd
-40 to +85 -40 to +125 260
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD).
Thermal Resistance
Parameters
Symbol Value Unit
Junction ambient SSO20
RthJA
140
K/W
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Common DC Characteristics
VSS = 0 V, Tamb = -40C to +85C unless otherwise specified
Parameters Power Supply Test Conditions/Pins Symbol Min. Typ. Max. Unit
Operating voltage at VBatt Operating voltage at VDD fSYSCL = 1 MHz Active current CPU active VDD = 2.0 V VDD = 3.0 V VDD = 6.5 V fSYSCL = 1 MHz Power down current (CPU sleep, RC oscillator active, 4-MHz quartz oscillator active) Sleep current (CPU sleep, 32-kHz quartz-oscillator inactive 4-MHz quartz-oscillator inactive) Reset current VDD = 2.0 V VDD = 3.0 V VDD = 6.5 V VDD = 6.5 V
VBatt VDD IDD
2.0 VPOR 200 300 600 1.0
6.5 6.5 250 800 70 400 2.0
V V A A A A A A A A
IPD
40 100 250
ISleep VDD < VPOR IReset
1.0 150
DC Characteristics - Microcontroller ATAR092
VSS = 0 V, Tamb = -40C to +85C unless otherwise specified
Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Brown-out Protection Reset Threshold Voltage
Reset threshold voltage Reset threshold voltage Reset hysteresis
Voltage Monitor Threshold Voltage
BOT = 1 BOT = 0
VPOR VPOR VPOR
155 1.85
1.7 2.0 50 3.0
1.85 2.2
V V mV
VM high threshold voltage VM high threshold voltage VM middle threshold voltage VM middle threshold voltage VM low threshold voltage VM low threshold voltage
External Input Voltage
VDD > VM, VMS = 1 VDD < VM, VMS = 0 VDD > VM, VMS = 1 VDD < VM, VMS = 0 VDD > VM, VMS = 1 VDD < VM, VMS = 0 VMS = 1, VDD = 3 V VMS = 0, VDD = 3 V
VMThh VMThh VMThm VMThm VMThl VMThl VVMI VVMI 1.2 2.0 2.4 2.8
3.25 2.8 2.4
V V V V V V
3.0 2.6 2.6 2.2 2.2 1.3 1.3 1.4
VMI rising edge threshold VMI falling edge threshold
V V
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DC Characteristics - Microcontroller ATAR092 (Continued)
VSS = 0 V, Tamb = -40C to +85C unless otherwise specified
Parameters All Bi-directional Ports Test Conditions/Pins Symbol Min. Typ. Max. Unit
Input voltage LOW Input voltage HIGH Input LOW current (pull-up) Input HIGH current (pull-down) Input LOW current (strong pull-up) Input LOW current (strong pull-down) Input leakage current Input leakage current
VDD = 1.8 V to 6.5 V VDD = 1.8 V to 6.5 V VDD = 2.0 V, VDD = 3.0 V, VIL= VSS VDD = 6.5 V VDD = 2.0 V, VDD = 3.0 V, VIH = VDD VDD = 6.5 V VDD = 2.0 V, VIL= VSS VDD = 6.5 V VDD = 2.0 V, VIH = VDD VDD = 6.5 V VIL= VSS VIH= VDD VOL = 0.2 VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V VOH = 0.8 VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V
VIL VIH IIL
VSS 0.8 VDD -2.0 -50 2.0 -4.0 -20 -100 4.0 20 100 -50 -600 50 600
0.2 VDD VDD -12 -200 12 200 -100 -1200 100 1200 100 100
V V A A A A A A A A A A nA nA mA mA mA mA mA mA
IIH 50 IIL IIH IIL IIH 0.6 IOL 8 -0.6 IOH -8 -20 -300 20 300
Output LOW current
1.2 5 15 -1.2 -5 -16
2.5 22 -2.5 -24
Output HIGH current
Note:
The BP20/NTE pin has a strong pull-up resistor during the reset-phase of the microcontroller.
16
U9280M-H
4591A-RFID-03/03
U9280M-H
AC Characteristics - Operation Cycle Time
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40C to +85C unless otherwise specified
Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit
System clock cycle
VDD = 1.8 V to 6.5 V Tamb = -40C to +85C VDD = 2.4 V to 6.5 V Tamb = -40C to +85C
tSYSCL tSYSCL
500 250
2000 2000
ns ns
Timer 2 Input Timing Pin T2I
Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH time
Timer 3 Input Timing Pin T3I
fT2I tT2IL tT2IH fT3I tT3IL tT3IH 2 tSYSCL 2 tSYSCL 100 100 100 100
5
MHz ns ns
Timer 3 input clock Timer 3 input LOW time Timer 3 input HIGH time
Interrupt Request Input Timing
SYSCL/2 ns ns
Interrupt request LOW time Interrupt request HIGH time
External System Clock
tIRL tIRH ECM = EN Rise/fall time < 10 ns ECM = DI Rise/fall time < 10 ns Rise/fall time < 10 ns VDD > VPOR
ns ns
EXSCL at OSC1 EXSCL at OSC1 Input HIGH time
Reset Timing
fEXSCL fEXSCL tIH tPOR fRcOut1
0.5 0.02 0.1 1.5 3.8
4 4
MHz MHz s
Power-on reset time
RC Oscillator 1
5
ms MHz
Frequency Stability Temperature coefficient
RC Oscillator 2 - External Resistor
VDD = 2.0 V to 6.5 V
Df/f Df/f/C
50 0.15 4 1 15 10 4 5 -10 0 0 +10 20 20
% %
Frequency Stability Stabilization time
Rext = 170 kW Rext = 720 kW VDD = 2.0 V to 6.5 V
fRcOut2 fRcOut2 Df/f tS fX tSQ
Df/f
MHz % s MHz ms ppm pF pF
4-MHz Crystal Oscillator (Operating Range 2.2 V to 6.5 V)
Frequency Start-up time Stability Integrated input/output capacitances (mask programmable) CIN/COUT programmable in steps of 2 pF
CIN COUT
17
4591A-RFID-03/03
AC Characteristics - Operation Cycle Time (Continued)
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40C to +85C unless otherwise specified
Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit 32-kHz Crystal Oscillator (Operating Range 2.0 V to 6.5 V)
Frequency Start-up time Stability Integrated input/output capacitances (mask programmable)
External 32-kHz Crystal Parameters
fX tSQ
Df/f
32.768 0.5 -10 0 0 32.768 30 1.5 3 4.0 40 1.4 3 150 3 50 +10 20 20
kHz s ppm pF pF kHz kW pF fF MHz
W
CIN/COUT programmable in steps of 2 pF
CIN COUT fX RS C0 C1 fX RS C0 C1
Crystal frequency Serial resistance Static capacitance Dynamic capacitance
External 4 MHz Crystal Parameters
Crystal frequency Serial resistance Static capacitance Dynamic capacitance
pF fF
Figure 8. Crystal and Equivalent Circuit
Equivalent Equivalent circuit circuit OSCIN OSCIN SCLIN SCLIN OSCOUT OSCOUT SCLOUT SCLOUT L L C1 C1 RS RS
C0 C0
18
U9280M-H
4591A-RFID-03/03
U9280M-H
DC Characteristics -Transponder Interface U3280M
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40C to +85C unless otherwise specified
Parameters Power Supply Test Conditions/Pins Symbol Min. Typ. Max. Unit
Operating voltage at VBatt Operating voltage at VDD during battery supply VDD limiter voltage during coil supply
Power Management
VBatt VDDB VDDC VDD > 1.8 V VDD > 1.8 V IS = 1 mA, VBatt = 2 V VFDon VFDoff VSD ICI VCU > 5 V VCMS CIN
2.0 VBattVSD 2.4 2.2 2.9 2.5 0.8
6.5
V V
3.2 2.9 300 20
V V V mV mA V pF
Field on detection voltage Field off detection voltage Voltage drop at power-supply switch
Coil Input Coil 1, Coil 2
Coil input current Coil voltage stroke during modulation Input capacitance
MOD Pin
1.8 30
4.0
Input LOW voltage Input HIGH voltage Input leakage current
NGAP/FC Pin
VIL VIH IIleak VDD = 2.0 V VOL = 0.2 VDD VDD = 2.0 V VOH = 0.8 VDD VDD = 2 V
VSS 0.8 VDD 10
0.2 VDD VDD
V V nA
Output LOW current Output HIGH current
EEPROM
IOL IOH
0.08 -0.06
0.2 -0.15
0.3 -0.25
mA mA
Operating current during erase/write cycle
IWR
450
A
19
4591A-RFID-03/03
AC Characteristics - Transponder Interface U3280M
Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V, Tamb = -40C to +85C unless otherwise specified
Parameters Serial Interface Timing (Internal) Test Conditions Symbol Min. Typ. Max. Unit
SCL clock frequency (intern)
Serial Timing (if SCL and SDA Available Extern)
fSC fSCL tLOW tHIGH tR tF tSUSTA tHDSTA tSUDAT tHDDAT tSUSTO tBUF tI tDH fCOIL VCoilGap < 0.7 VDC VCoilField > 3 VDC tFGAP0 tFGAP1 tBFS tFBS Erase/write-cycles for 16 bits access 10 1 160 10 300 125 4.7 4.0 250 0 4.7 4.7 0 4.7 4.0
500 100
kHz kHz s s
SCL clock frequency (extern) Clock low time Clock high time SDA and SCL rise time SDA and SCL fall time Start condition setup time Start condition hold time Data input setup time Data input hold time Stop condition setup time Bus free time Input filter time Data output hold time
Coil Inputs
1000 300
ns ns s s ns ns s s
100 1000
ns ns kHz
Coil frequency
Gap Detection
Delay field off to gap = 0 Delay field on to gap = 1
Power Management
50 10 650 60
s s s ms E/Wcycles
Battery to field switch delay Field to battery switch delay
EEPROM
Endurance Data erase/write cycle time Data erase time Data retention time Power-up to read operation Power-up to write operation
ED tDEW tDE
500,000
1,000,000 9 12 1/2 tDEW
ms ms years
2 10
Tamb = 25C
tDR tPUR tPUW
0.2 0.2
ms ms
20
U9280M-H
4591A-RFID-03/03
U9280M-H
Ordering Information
Please select the option settings from the list below and insert in ROM CRC.
Output Port 1 BP10 [X] CMOS [X] Pull-up [ ] Open drain [N] [ ] Open drain [P] BP13 [X] CMOS [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [X] Pull-up BP51 [X] CMOS [ ] Open drain [N] [ ] Open drain [P] Port 2 BP20 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP21 [X] CMOS [ ] Pull-up [ ] Pull-down [ ] Pull-up strong BP53 [ ] CMOS [X] Pull-up [ ] Open drain [N] [ ] Open drain [P] Port 6 BP60 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP63 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong OSC1 [ ] No integrated capacitance [ ] Internal capacitance [ _____pF] OSC2 [ ] No integrated capacitance [ ] Internal capacitance [ _____pF] ECM (External Clock Monitor) [ ] Enable [ ] Disable [ ] Open drain [N] [ ] Open drain [P] BP22 [X] CMOS [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [X] Pull-up [ ] Open drain [N] [ ] Open drain [P] BP23 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] Port 4 BP40 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP41 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP42 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] BP43 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong BP52 [X] CMOS [ ] Open drain [N] [ ] Open drain [P] [ ] Open drain [N] [ ] Open drain [P] Input Port 5 BP50 [ ] CMOS [ ] Open drain [N] [ ] Open drain [P] [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [X] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [X] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong [ ] Pull-up [ ] Pull-down [ ] Pull-up strong [ ] Pull-down strong Output Input
File: _____________________ . HEX Aproval Date: _________________
CRC: ____________________ . HEX Signature: _________________________
21
4591A-RFID-03/03
Ordering Information (Continued)
Extended Type Number Package Remarks
U9280M-H-xxxz-FSG3
SSO20
> 200 kpcs annually taped and reeled
Customer ROM mask - To be defined by the customer - Lead time: 18 weeks after ROM mask programming and reception of the order Flash Version: As flash version of the U9280M-H the MARC4 ATAR892 is used (available from stock).
Package Information
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications
1
10
22
U9280M-H
4591A-RFID-03/03
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4591A-RFID-03/03 xM

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